Semiconductor Deposition Process
The thin film deposition of different materials is one of the most critical steps in the manufacturing process of semiconductor devices. The on-going integration into the third dimension is presenting new and increasingly challenging requirements to the deposition processes. Especially uniformity over the full wafer area and the capability to deposit material uniformly on 3D structures in the nanometer scale are key drivers for new developments and requirements within the semiconductor manufacturing equipment.
The challenges faced in modern deposition processes are uniformity of layers, temperature and gas flow. The need to avoid particle generation and process contamination to achieve high process yields is also of paramount importance.
To address the challenges of uniformity within the process it is crucial to control temperature and gas flow. Gas flow is controlled by tubes with tight dimensional tolerances and optimized design of the quartz ware. For improved thermal management Heraeus offers a unique opaque material solution.
A primary cause of particle generation in plasma-supported deposition processes is linked to the bubble content of the quartz base material. Heraeus has developed a wide portfolio of low bubble content material helping to address this challenge.
Impurities within the quartz ware have become a growing concern due to shrinking node sizes in semiconductor manufacturing. Heraeus manufactures high purity and synthetic quartz materials and fabricated solutions to counter this concern.
Batch Processing
For processes requiring long runtimes, it is desirable to process more than one wafer at the same time. This is called batch processing. Typically processes from the area of chemical vapor deposition can be used in batch processing, including PECVD, ALD or PEALD. Batch deposition processes are typically carried out inside vertical or horizontal tube furnaces. Wafers are loaded inside so-called wafer boats into the batch furnace system. Such systems can handle 100 to 160 (in some cases even more) in one process run.
Epitaxy
A very special case of a deposition process is the so-called epitaxial deposition, or simply Epitaxy. This process is designed to deposit material onto a single-crystal template, growing as a single crystal layer. One of the first steps in the manufacturing chain of semiconductor devices is the deposition of epitaxial silicon onto the blank silicon wafer. This is done in an epitaxy process. Very often these processes are run with only one wafer being processed at a time (i.e. Single Wafer Processing) or in small numbers (i.e. Multi-wafer or Mini-batch).
Semiconductor Etching Process
Besides lithography and deposition processes, one of the most critical processes in the semiconductor manufacturing chain is the etching process. For the ongoing 3D integration of more and more semiconductor devices, especially DRAM and NAND Flash, plasma etching processes are the turnkey process to enable higher integration density and shrinking feature sizes. High aspect ratios between the lateral dimensions of the etch structure and the etch depth are required for leading edge processes.
For single wafer plasma etching processes the requirements can be versatile, but especially uniformity over the full wafer area is a critical point to influence the product yield for the semiconductor chip manufacturer. The ability to etch one material selective in all directions (isotropic) and not only in one direction (anisotropic) is becoming an important process requirement especially during the manufacturing of multi layer NAND flash devices.
Time between services impacts the uptime of your etching and ashing tools. A primary cause for tool down maintenance is particle levels exceeding predefined thresholds. Bubbles within the quartz ware contribute to particle generation in plasma etching processes. This is a growing concern as shrinking node sizes drive smaller acceptable particle sizes and counts.
Heraeus has focused on developing cost-effective low bubble materials to specifically address this challenge.
Microlithography
Since the invention of integrated circuits (semiconductor chips) microlithography is the key process step of the manufacturing chain for electronics. In this step light is used to structure silicon or other semiconducting materials by imaging the tiny structures of a reticle (mask) onto the wafer that has been coated with a photo resist. After development this photo resist acts as a template for the subsequent processes, like doping and etching, needed to alter locally the electronic properties of the semiconductor. This functionalisation of the wafer is the base for the generation of all the electronic units (transistors, capacitors,…) on the chip.
The ongoing trend to miniaturise integrated circuits (Moore’s Law) requires extremely precise optical imaging of the mask onto the wafer with minimal aberrations close to theoretical limits. The tiniest structures of high-end chips have only a width of less than one tenth of the used wavelength! The optical design and the manufacturing of such projection optics modules (s. photo) are the most challenging in optics.
Besides the quality of the optics, the imaging wavelength plays a critical role. Because the minimum feature size of an imaged structure gets smaller with shorter wavelengths, modern semiconductor chips are produced using ArF excimer laser as a light source with a wavelength of 193 nm (deep UV: DUV)).
The optical material of choice for microlithography optics is synthetic fused silica, because it supports perfectly the above mentioned demands for an aberration free DUV optical system. Synthetic fused silica has a very high DUV transmissivity and low absorption, so that no image defects due to lens heating occur. It can be produced with excellent optical 3D homogeneity (low refractive index variations) and negligible stress birefringence. An additional requirement for the optical material is the durability against UV radiation. Although the pulse energy densities used in microlithography steppers are relatively low (< 1 mJ/cm²), only optimized fused silica types keep their excellent initial properties during the expected lifetime of approximately 10 years operation.
